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? semiconductor components industries, llc, 2002 june, 2002 rev. 5 1 publication order number: mc10ep445/d mc10ep445, mc100ep445 3.3v/5vecl 8-bit serial/parallel converter the mc10/100ep445 is an integrated 8bit differential serial to parallel data converter with asynchronous data synchronization. the device is designed to operate for nrz data rates of up to 2.5 gb/s. the conversion sequence was chosen to convert the first serial bit to q0, the second bit to q1, etc. two selectable differential serial inputs, which are selected by sinsel, provide this device with loopback testing capability. the mc10/100ep445 has a sync pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from d n to d n+1 . each additional shift requires an additional pulse to be applied to the sync pin. control pins are provided to reset and disable internal clock circuitry. additionally, v bb pin is provided for singleended input condition. the 100 series contains temperature compensation. ? 300 ps propagation delay ? 2.5 gb/s data rate ? differential clock and serial inputs ? v bb output for single-ended input applications ? asynchronous data synchronization (snyc) ? asynchronous master reset (reset) ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 5.5 v ? open input default state ? safety clamp on inputs ? clk enable immune to runt pulse generation lqfp32 fa suffix case 873a marking diagram* mcxxx awlyyww xxx = 10 or 100 a = assembly location wl = wafer lot yy = year ww = work week ep445 *for additional information, see application note and8002/d device package shipping ordering information mc10ep445fa lqfp32 250 units/tray mc10ep445far2 lqfp32 2000/tape & reel mc100ep445fa lqfp32 250 units/tray mc100ep445far2 lqfp32 2000/tape & reel 32 1 http://onsemi.com
mc10ep445, mc100ep445 http://onsemi.com 2 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 figure 1. 32lead lqfp pinout (top view) warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin description pin sina*, sina * function ecl differential serial data input a sinsel* q0q7 ecl parallel data outputs ecl serial input selector pin clk*, clk * ecl differential clock inputs pclk, pclk ecl differential parallel clock output sync* ecl conversion synchronizing input cksel* ecl clock input selector pin v bb0 , v bb1 output reference voltage v cc positive supply v ee negative supply v cc pclk q0 v cc v cc sinsel v cc v ee sina reset sync sinb v ee q3 q4 q5 q6 q7 mc10ep445 mc100ep445 pclk q1 q2 v cc sinb v bb0 sina v cc cken clk clk v bb1 cksel v cc sinb*, sinb * ecl differential serial data input b cken * ecl clock enable pin reset* ecl reset pin * pins will default logic low or differential logic low when left open. truth table function pin high low sinsel select sinb input select sina input cksel q: pclk = 8:1 clk: q = 1:1 q clk q: pclk = 8:1 clk: q = 1:2 q clk cken synchronously disable internal clock circuitry synchronously enable internal clock circuitry reset asynchronous master reset synchronous enable sync asynchronously applied to swallow a data bit normal conversion process
mc10ep445, mc100ep445 http://onsemi.com 3 figure 2. logic diagram q0 1:2 demux 1:2 demux 1:2 demux 1:2 demux q4 q2 q6 q1 q5 q3 q7 1:2 demux 1:2 demux 1:2 demux div2 div2 pclk pclk sina sina sinb sinb sinsel t c q r cksel t c q r cken clk clk reset sync control logic v ee attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity (note 1) level 2 flammability rating oxygen index: 28 to 34 ul 94 v0 @ 0.125 in transistor count 993 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc10ep445, mc100ep445 http://onsemi.com 4 maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 32 lqfp 32 lqfp 80 55 c/w c/w q jc thermal resistance (junctiontocase) std bd 32 lqfp 12 to 17 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 10ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mv v ol output low voltage (note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mv v ih input high voltage (singleended) 2090 2415 2155 2480 2215 2540 mv v il input low voltage (singleended) 1365 1690 1460 1755 1490 1815 mv v bb output voltage reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mv v ihcmr input high voltage common mode range (differential) (note 5) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 ohms to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep445, mc100ep445 http://onsemi.com 5 10ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 7) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 8) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mv v ol output low voltage (note 8) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mv v ih input high voltage (singleended) 3790 4115 3855 4180 3915 4240 mv v il input low voltage (singleended) 3065 3390 3130 3455 3190 3515 mv v bb output voltage reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mv v ihcmr input high voltage common mode range (differential) (note 9) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 7. required 500 lfpm air flow when using +5 v power supply. for (v cc v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.3 v. 8. all loading with 50 ohms to v cc 2.0 volts. 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 10ep dc characteristics, necl v cc = 0 v, v ee = 5.5 v to 3.0 v (note 10) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 11) 95 119 143 98 122 146 100 125 150 ma voh output high voltage (note 12) 1135 1010 885 1070 945 820 1010 885 760 mv v ol output low voltage (note 12) 1935 1810 1685 1870 1745 1620 1810 1685 1560 mv v ih input high voltage (singleended) 1210 885 1145 820 1085 760 mv v il input low voltage (singleended) 1935 1610 1870 1545 1810 1485 mv v bb output voltage reference 1510 1410 1310 1445 1345 1245 1385 1285 1185 mv v ihcmr input high voltage common mode range (differential) (note 13) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. input and output parameters vary 1:1 with v cc . 11. required 500 lfpm air flow when using 5 v power supply. for (v cc v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.3 v. 12. all loading with 50 ohms to v cc 2.0 volts. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep445, mc100ep445 http://onsemi.com 6 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 14) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 15) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 15) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ih input high voltage (singleended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (singleended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential) (note 16) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 14. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 15. all loading with 50 ohms to v cc 2.0 volts. 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 17) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 18) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 19) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mv v ol output low voltage (note 19) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mv v ih input high voltage (singleended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (singleended) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mv v ihcmr input high voltage common mode range (differential) (note 20) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 17. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 18. required 500 lfpm air flow when using +5 v power supply. for (v cc v ee ) >3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.3 v. 19. all loading with 50 ohms to v cc 2.0 volts. 20. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc10ep445, mc100ep445 http://onsemi.com 7 100ep dc characteristics, necl v cc = 0 v, v ee = 5.5 v to 3.0 v (note 21) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current (note 22) 95 119 143 98 122 146 100 125 150 ma v oh output high voltage (note 23) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 23) 1945 1820 1695 1945 1820 1695 1945 1820 1695 mv v ih input high voltage (singleended) 1225 880 1225 880 1225 880 mv v il input low voltage (singleended) 1945 1625 1945 1625 1945 1625 mv v bb output voltage reference 1525 1425 1325 1525 1425 1325 1525 1425 1325 mv v ihcmr input high voltage common mode range (differential) (note 24) v ee + 2.0 0.0 v ee + 2.0 0.0 v ee + 2.0 0.0 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 21. input and output parameters vary 1:1 with v cc . 22. required 500 lfpm air flow when using 5 v power supply. for (v cc v ee ) > 3.3 v, 5 to 10 in line with v ee required for maximum thermal protection at elevated temperatures. recommend v cc v ee operation at 3.3 v. 23. all loading with 50 to v cc 2.0 volts. 24. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 25) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 12. f max /jitter) 2.5 2.5 2.5 ghz t plh , t phl propagation delay to clk to q output differential clk to pclk 1230 1000 1450 1240 1660 1490 1300 1050 1530 1310 1760 1580 1400 1140 1650 1420 1900 1710 ps ts setup time clk to sina, b (figure 4) clk to cken (figure 5) 400 60 ps t h hold time clk to sina, b (figure 4) cken to clk (figure 5) 600 80 ps t rr /t rr2 reset recovery (figure 3) 350 180 350 180 350 180 ps t pw minimum pulse width reset 400 400 400 ps t jitter cycletocycle jitter (see figure 12. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (differential) (note 26) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times q (30% 70%) 100 180 250 100 200 300 125 230 325 ps 25. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc 2.0 v. 26. v pp (min) is the minimum input swing for which ac parameters are guaranteed.
mc10ep445, mc100ep445 http://onsemi.com 8 figure 3. reset recovery reset clk t rr clk figure 4. setup and hold time t h t s sina, sinb + 0 clk figure 5. setup and hold time for cken data valid t s clk t h cken
mc10ep445, mc100ep445 http://onsemi.com 9 application information the mc10/100ep445 is an integrated 1:8 serial to parallel converter. either of the two differential input serial data path provided for this device, sina and sinb, can be chosen with the sinsel pin (pin 25). sina is the default input path when sinsel pin is left floating. because of internal pulldowns on the input pins, all input pins will default to logic low when left open. the two selectable serial data paths can be used for loopback testing as well as the bit error testing. upon powerup, the internal flipflops will attain a random state. to synchronize multiple flipflops in the device, the reset (pin 1) must be asserted. the reset pin will disable the internal clock signal irrespective of the cken state (cken disables the internal clock circuitry). the device will grab the first stream of data after the falling edge of reset , followed by the falling edge of clk , on second rising edge of clk in either cksel modes. (see figure 6) clk reset pclk reset (asynchronous reset) reset (synchronous enable) figure 6. reset timing diagram
mc10ep445, mc100ep445 http://onsemi.com 10 the cksel (pin 7) input is provided to enable the user to select the serial data rate input between internal clock data rate or twice the internal clock data rate. for cksel low operation, the data is latched on both the rising edge and the falling edge of the clock and the time from when the serial data is latched to when the data is seen on the parallel output is 6 clock cycles (see figure 7). figure 7. timing diagram a. 1:8 serial to parallel conversion with cksel low clk sina reset cksel pclk q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 q1 q2 q3 q4 q5 q6 q7 d0 d8 d16 d1 d9 d17 d2 d10 d18 d3 d11 d19 d4 d12 d20 d5 d13 d21 d6 d14 d22 d7 d15 d23 cken 123456 number of clock cycles from data latch to q
mc10ep445, mc100ep445 http://onsemi.com 11 similarly, for cksel high operation, the data is latched only on the rising edge of the clock and the time from when the serial data is latched to when the data is seen on the parallel output is 12 clock cycles (see figure 8). figure 8. timing diagram a. 1:8 serial to parallel conversion with cksel high clk sina reset cksel pclk q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 cken 123456 number of clock cycles from data latch to q 7 8 9 10 11 12
mc10ep445, mc100ep445 http://onsemi.com 12 to allow the user to synchronize the output byte data correctly, the start bit for conversion can be moved using the sync input pin (pin 2). asynchronously asserting the sync pin will force the internal clock to swallow a clock pulse, ef fectively shifting a bit from the q n to the q n1 output as shown in figure 9 and figure 10. for cksel low, a single pulse applied asynchronously for two consecutive clock cycles shifts the start bit for conversion from q n to q n1 . the bit is swallowed following the two clock cycle pulse width of sync on the next triggering edge of clock (either on the rising or the falling edge of the clock). each additional shift requires an additional pulse to be applied to the sync pin. (see figure 9) figure 9. timing diagram a. 1:8 serial to parallel conversion with sync pulse at cksel low clk sina cksel pclk sync q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 q1 q2 q3 q4 q5 q6 q7 d0 d9 d17 d1 d10 d18 d2 d11 d19 d3 d12 d20 d4 d13 d21 d5 d14 d22 d6 d15 d23 d7 d16 d24 12 2 clock cycles for sync next triggering edge of clock bit d8 is swallowed
mc10ep445, mc100ep445 http://onsemi.com 13 for cksel high, a single pulse applied asynchronously for three consecutive clock cycles shifts the start bit for conversion from q n to q n1 . the bit is swallowed following the three clock cycle pulse width of sync on the next triggering edge of clock (on the rising edge of the clock only). each additional shift requires an additional pulse to be applied to the sync pin. (see figure 10) figure 10. timing diagram a. 1:8 serial to parallel conversion with sync pulse at cksel high 12 3 clock cycles for sync next triggering edge of clock bit d8 is swallowed clk sina pclk q0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 q1 q2 q3 q4 q5 q6 q7 d0 d1 d2 d3 d4 d5 d6 d7 sync 3
mc10ep445, mc100ep445 http://onsemi.com 14 the synchronous cken (pin 3) applied with at least one clock cycle pulse length will disable the internal clock signal. the synchronous cken will suspend all of the device activities and prevent runt pulses from being generated. the rising edge of cken followed by the falling edge of clk will suspend all activities. the first data bit will clock on the rising edge, since the falling edge of cken followed by the falling edge of the incoming clock triggers the enabling of the internal process. (see figure 11) clk pclk internal clock disabled internal clock enabled figure 11. timing diagram with cken with cksel high cksel cken the differential pclk output (pins 22 and 23) is a word framer and can help the user to synchronize the parallel data outputs. during cksel low operation, the pclk will provide a divide by 4clock frequency, which frames the serial data in period of pclk output. likewise during cksel high operation, the pclk will provide a divide by 8clock frequency. the v bb pin, an internally generated voltage supply, is available to this device only. for singleended input conditions, the unused differential input is connected to vbb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor, which will limit the current sourcing or sinking to 0.5ma. when not used, v bb should be left open. also, both outputs of the differential pair must be terminated (50 to v tt = v cc 2 v) even if only one output is used.
mc10ep445, mc100ep445 http://onsemi.com 15 v tt = v cc 2.0 v driver device receiver device qd 50 50 v tt q d 0 100 200 300 400 500 600 700 800 900 1000 0 500 1000 1500 2000 2500 3000 figure 12. f max /jitter input clk frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) 9 10 (jitter) figure 13. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc10ep445, mc100ep445 http://onsemi.com 16 package dimensions lqfp fa suffix 32lead plastic package case 873a02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 t z u t-u 0.20 (0.008) z ac t-u 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z t-u m 0.20 (0.008) z ac notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -ab- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -t-, -u-, and -z- to be determined at datum plane -ab-. 5. dimensions s and v to be determined at seating plane -ac-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -ab-. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10ep445/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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